& computational lithography[C&SI FAB]
Chips & Superintelligence Labs is an AI research lab building fab digital twins and AI systems for semiconductor manufacturing and computational lithography. We build tomorrow’s High-NA modeling and stitching, mask synthesis, 3D systems, wafer-scale lithography and hybrid bonding as digital twins today, and co-design their hardware and software there with the researchers and engineers who will run them.
A 50-second film. A camera zooms from a 300 mm wafer into one chip and its transistors. The chip appears as a closed die with bond pads on top, then opens into its layers in 3D: silicon, gate-all-around nanosheet transistors, contacts, and metal and via layers above them. An EUV scanner prints one layer: a laser pulse flattens a tin droplet and a second vaporises it, the plasma gives off 13.5 nm light, a collector focuses it, facet mirrors shape it, the reflective mask sends the pattern through six projection mirrors, and the wafer is scanned field by field while about 3% of the light arrives. A bridge between two lines appears and the chip is scrapped. C&SI Fab’s physics simulation, Neural Operators and RL are shown in turn. Full-chip ILT, computed as a real optimisation, reshapes the mask into curved shapes over a hundred iterations while the pattern error falls from about a fifth to a few percent and the missing contacts print, then the whole chip is corrected tile by tile. Back in the chip, the misprint is removed and the layer prints clean, and every chip on the wafer comes up good. The film ends on the Chips & Superintelligence Labs wordmark and C&SI Fab.
Tomorrow’slithography,built today
Better chips make better AI. Better AI can make better chips.
That loop runs through the fab. Chip design already has agents. The mask and the scanner under it do not. The next lithography tilts the light, halves the field and spends fewer photons on every feature, and there is no open model of it an agent could learn in. We are building one.
- 13.5nm
- The wavelength of the EUV light that prints the most advanced chips
- 0.55NA
- High-NA EUV optics, 4× across and 8× along the scan
- 26 × 16.5mm
- The half field one High-NA exposure prints. Bigger chips are stitched.
- 1 in 10⁹
- How rare the defects that decide yield can be
From the scanner to the stitched chip.
EUV light is so short that air absorbs it. High-NA tilts it further, halves the field and spends fewer photons on every feature, so the defects that kill yield become random, rare and new. We model that machine in software, so the work starts before the wafers do.
Tune everything at once.
Source, mask, dose and focus are tuned one after another today, often by different teams. The best result comes from moving them together. That search is too big for people and the right size for an agent.
Fast physics inside. An agent outside.
The inner loop is ours: an engine and a twin that answer in seconds and agree with the reference. The outer loop is an agent that sets up the experiment, reads one number and changes the setup or the code. More compute in, better masks and recipes out.
- Inner loop
- The forward engine and the twin, with adjoint and RL optimizers. Seconds to milliseconds per step.
- Outer loop
- A language-model agent that designs the experiment, sets the cost and rewrites the engine when it helps.
- One metric
- The probability that a chip prints across the process window, stitch included.
Work with us
hello@chipsuperintelligence.com- TalentJoin the teamLithography physicists, CUDA and numerical engineers, and RL researchers who want to change how chips are made.See open roles
- Chip manufacturersBuild with usBringing up High-NA or a stitched AI chip? Calibrate the twin on your data and run the agent on your hardest layer.Start a conversation
- Research labsPartner with usUniversity fabs and research labs with real wafers and hard patterning problems.Become a partner